Show HN: BPU – An embedded scheduler for stable UART pipelines https://ift.tt/ySmptwR

Show HN: BPU – An embedded scheduler for stable UART pipelines I recently came across this small ESP32 project and found the design ideas behind it very interesting. BPU (Batch Processing Unit) is a lightweight embedded scheduling core focused on keeping output pipelines stable under pressure (UART backpressure, limited bandwidth, bursty producers). Instead of blocking or growing unbounded queues, it: enforces per-tick byte budgets, coalesces redundant events, degrades gracefully under sustained load, exposes detailed runtime statistics. The repository includes design notes, flow diagrams, and real execution logs, which makes the runtime behavior very transparent. Repo: https://ift.tt/tBxKunQ I’ve been working on an ESP-IDF backend for it, and reading through the docs gave me a lot of ideas about observability and backpressure handling in small systems. Curious what others think about this approach. February 1, 2026 at 02:19AM